1. Field of the Invention
The invention relates to data transfer control systems for routing data between mass storage devices and main memory in a data processing system, and more particularly to a synchronization logic control system for multiplexing bus control between a hardware control system and a firmware control system without incurring data errors or affecting the data transfer rate.
2. Prior Art
In data processing systems wherein a plurality of functional units are electrically coupled by a common communication bus, extremely complex hardware and firmware synchronization control systems have been required to share the common bus between hardware and firmware during a high data rate transfer. When unsolicited bus requests requiring firmware interaction have occurred during the data transfer, the synchronization control systems have been required to track the data at the byte level in order to assure that no underrun or overrun errors occur when the firmware is allowed to access the common bus. As the data transfer rate increases, the timing of the synchronization control system becomes more critical and additional complexity in the control system network has been required. In seeking alternatives to the added complexity, system designers have had to sacrifice the data transfer rates.
The present invention is directed to a simplistic synchronization control system wherein the data transfer on a common communication bus may be interrupted for firmware accommodation of unsolicited bus requests without incurring data errors or affecting the transfer rate. The need for complex logic circuitry or increased firmware control storage is obviated.